In the fabrication of semiconductor devices, in order to stabilize and improve the yield of the devices, it is required to inhibit degradation of the characteristics and reliability of the devices. Factors of degradation of the characteristics and reliability of the devices include an increase in leak current caused by occurrence of crystal defect and degradation of the film quality of the gate oxide film, which are based on contamination of metal impurities.
As a measure against contamination of metal impurities, such a method is employed that forms a gettering site for metal impurities on a silicon semiconductor substrate constituting a semiconductor device. As this method, IG (Intrinsic Getter) method and EG (Extrinsic Getter) method have been conventionally well known.
The IG method is such a method that by subjecting the silicon semiconductor substrate to high-temperature heat treatment, oxygen on the surface of the silicon semiconductor substrate is diffused outwardly to form a non-crystalline defect layer (DZ layer: Denuded Zone) that is possibly to be a device forming region as well as forming, further inward of the substrate than the DZ layer, a BMD (Bulk Micro Defect) made of an oxygen precipitates as a gettering site.
The EG method is such a method that by introducing lattice distortion or defect on the back surface of the silicon semiconductor substrate, gettering of metal impurities is carried out. As a representative example, such a method is known that a gettering site is formed by providing mechanical damage by sand blasting, by causing a lattice misfit dislocation to occur by diffusing impurities such as phosphorus, or by forming a polysilicon film.
Now, also in a device required to have laminated device chips and extremely thin chips in the IC card and the like, a gettering site for metal impurities needs to be formed.
FIG. 11 shows a relationship between a DZ layer 3 and a BMD layer 4 of a conventional, 725-μm thick silicon semiconductor substrate 1 that is subjected to IG processing. Even in the case of forming the device forming region within the depth of approximately 5 μm from the surface of the silicon semiconductor substrate 1, by the IG method, the DZ layer 3 in the silicon semiconductor substrate 1 is formed to have a width of equal to or more than 10 μm. When the IC chip is thick (e.g., the thickness of the silicon semiconductor substrate 1 being 725 μm), if the number of the BMD 2 formed in the silicon semiconductor substrate 1 is approximately 1×105/cm2 (hereinafter abbreviated as 1E+05, this abbreviation on the basis of the assumption that m×10n is denoted as mE+n being used in examples described below), then a sufficient ability of gettering of metal impurities is possessed.
However, when, due to lamination of device chips and in IC cards and the like, the IC chip is as extremely thin as equal to or less than 100 μm, then the number of the BMD 2 in the silicon semiconductor substrate is significantly smaller than when the IC chip is thick.
FIG. 12 shows a relationship between the DZ layer 3 and the BMD layer 4 in the case of processing the silicon semiconductor substrate 1 to 50 μm thick to fabricate an IC chip of as extremely thin as 50 μm. In the silicon semiconductor substrates 1 shown in FIGS. 11 and 12 for comparison, when proportional calculations for the number of the BMD 2 are carried out on the basis of the thicknesses of the BMD layers 4, the number of the is BMD 2 in the case of the 50-μm thickness (the forming region in the BMD 2 being 40 μm) is as small as 6% of that in the case of 725-μm thickness (the forming region in the BMD being 705 μm).
FIG. 13 shows, in the silicon semiconductor substrate 1 shown in FIG. 12, the distribution of the number of the BMD 2 in the depth direction from the substrate surface. As shown in FIG. 13, the BMD is formed from the depth of 10 μm, and the number of the BMD is small in the depth of from 10 to 20 μm. It is from the depth of from 20 to 30 μm from the surface that 1E+05/cm2 is reached, where a sufficient ability of gettering is possessed.
The gettering ability of metal impurities depends on the number of the BMD 2. An extremely thinner IC chip is more largely affected by the width of the DZ layer 3. That is, as the width of the DZ layer 3 becomes larger, the number of the BMD 2 becomes smaller, thus largely reducing the gettering ability of metal impurities.
FIG. 14 shows a relationship between the DZ layer 3 and the BMD layer 4 in the case of forming a 5-μm epitaxial Si layer 5 as a device forming region in the silicon semiconductor substrate 1 of an IC chip of as extremely thin as 50 μm. Referring to FIG. 14, when the Si layer 5, which is a non-crystalline defect layer, is epitaxial-grown as a device forming region on a silicon semiconductor substrate where the thickness of the DZ layer 3 is equal to or more than 10 μm, then the thickness of the epitaxial-grown Si layer 5 is added, and thus the use of an extremely thin IC chip further decreases the number of the BMD 2 compared with the case where the epitaxial Si layer 5 is not grown.
FIG. 15 shows the distribution of the number of the BMD in FIG. 14 in the depth direction from the substrate surface. As shown in FIG. 15, compared with the case of not growing the epitaxial Si layer 5, the point where formation of the BMD 2 starts is deeper by the degree equivalent to the thickness of the epitaxial Si layer 5; consequently, the BMD starts being formed from the depth of 15 μm. In the depth of from 15 to 25 μm, the number of the BMD is small, and it is from the depth of from 25 to 35 μm from the surface that the number of the BMD reaches 1E+05/cm2, where a sufficient ability of gettering is possessed. The number of the BMD is approximately 15% smaller than that in the case of not growing the epitaxial Si layer 5.
A method is known (see, for example, patent document 1) such that referring to FIG. 16(A), a Si layer 22 is epitaxial-grown on a silicon semiconductor substrate 21, after which, referring to FIG. 16(B), heat treatment is carried out to form an oxygen precipitates 23. Referring to 16(C), heat treatment is further carried out to make a BMD 23a inside the silicon semiconductor substrate 21. In this method, however, oxygen on the surface of the silicon semiconductor substrate 21 under the epitaxial Si layer 22 is externally diffused, after which a non-crystalline defect region is formed, and thus the use of an extremely thin IC chip further decreases the number of the BMD 23a. 
In the EG method, if the IC chip is as extremely thin as equal to or less than 100 μm, it is difficult in terms of strength to introduce lattice distortion or defect on the back surface. If the back surface of the silicon semiconductor substrate is subjected to mechanical grinding, the back surface becomes rough, which leads to introduction of defect to generate the EG effect of gettering of metal impurities. However, if the silicon semiconductor substrate becomes extremely thin, the bending strength of the substrate becomes weak, and thus if the back surface is rough, the substrate becomes easy to crack. In order to enhance the bending strength and prevent cracking, the back surface of the silicon semiconductor substrate needs to be processed into mirror. However, mirror processing eliminates the EG effect of gettering of metal impurities, which leads to, due to contamination of metal impurities, degradation of device characteristics and reliability.
Patent document 1: Japanese Patent Application Publication No. 4-43646.